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Power minimisation of VLSI wave digital filters through systolic block size selection

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2 Author(s)
Israsena, P. ; Sch. of Eng., Warwick Univ., Coventry, UK ; Summerfield, S.

An investigation into systolic architectures for wave digital filters for low-power applications is presented. Based on a three-port adaptor implementation of the second-order section, minimum power is found using pipelining with a 2 bit block size for which the power consumption is reduced by 50% and the power-area-delay performance increased by 5 times relative to the starting, non-pipelined, implementation

Published in:

Electronics Letters  (Volume:35 ,  Issue: 21 )