By Topic

Method for switching noise reduction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Raič, D. ; Fac. of Electr. Eng., Ljubljana Univ., Slovenia

A method is proposed for reducing digital noise in mixed analogue-digital CMOS circuits. The method is based on a distributed clock driver and reverse clocking technique. It is best suited to circuits where speed can be traded for noise reduction. Reduction factors depend on the circuit design and speed limitations; values in the range 10-50 can be achieved in most cases

Published in:

Electronics Letters  (Volume:35 ,  Issue: 21 )