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Method for switching noise reduction

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1 Author(s)
D. Raic ; Fac. of Electr. Eng., Ljubljana Univ., Slovenia

A method is proposed for reducing digital noise in mixed analogue-digital CMOS circuits. The method is based on a distributed clock driver and reverse clocking technique. It is best suited to circuits where speed can be traded for noise reduction. Reduction factors depend on the circuit design and speed limitations; values in the range 10-50 can be achieved in most cases

Published in:

Electronics Letters  (Volume:35 ,  Issue: 21 )