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Datapath layout compiler using bit-wise cell-sizing scheme for delay balancing and power minimisation

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2 Author(s)

While existing datapath compilers generate the same size buffer for all bits, in real datapaths the load capacitance fluctuates according to the bit position, which leads to a nonuniform bit delay with unnecessarily high power consumption. This Letter proposes a datapath layout compiler using a bit-wise cell sizing scheme that reduces the power consumption by equalising the delay of each bit position to the critical bit delay. Experimental results using the example of a real microprocessor have demonstrated a power consumption saving using the tri-state bus of 12% on average, compared to conventional datapaths using a uniform-size cell

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Electronics Letters  (Volume:35 ,  Issue: 21 )