A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver

A transceiver for multibit-rate digital subscriber loop is presented with up to 25-kft reach on using AWG 24 wire. An adjustable data rate from 160 to 768 kb/s is employed to achieve N/spl times/64 kb/s voice channel (N=2-12). The IC contains a 14-bit, 63 dual current sources multibit /spl Sigma//spl Delta/ digital-to-analog converter with "hopping" dynamic elements, a /spl Sigma//spl Delta/ analog-to-digital converter (ADC), and an on-chip high-swing nested Miller line driver; and for full duplex communication an integrated -30 dB rejection hybrid filter based on line and transformer parasitics matching. The concept has been tested using two sets of silicon test chips, one for symmetrical digital subscriber line (SDSL) and one for asymmetrical DSL (ADSL), on a line emulator with and without additive line noise for SDSL and ADSL rates (line driver external for ADSL with fourth-order multibit ADC for ADSL). In the analog front end, supply is 3 V for all the digital blocks, including the interface to the digital portion of the DSL, and 5 V for all the analog blocks. Power is 250 mW, with 12-mm/sup 2/ area. The transceiver can cover the full set of ANSI T1.601 basic rate ISDN (UkO-interface) loops while providing 2.5 times the throughput of existing U-interface transceivers. Nearly five times the throughput (768 kb/s) can be achieved even in the presence of worst case self-crosstalk. The additional performance is achieved by using a combination of coding, digital, and analog techniques.