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A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems

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3 Author(s)
Scheytt, J.C. ; Lehrstuhl fur Elektron. Bauelemente, Ruhr-Univ., Bochum, Germany ; Hanke, Gerhard ; Langmann, Ulrich

This paper presents a 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery circuit for transparent synchronous digital hierarchy (SDH) systems. The IC incorporates a clock and data recovery phase-locked loop (PLL), a bit-rate detection circuit, and a reference PLL. A bit-rate detection circuit detects the instantaneous bit rate and switches the clock and data recovery PLL. The circuit was designed in a 25-GHz fT Si-bipolar transistor array and dissipates 680 mW from -5 V supply voltage. Jitter performance is compliant with SDH/SONET specifications

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 12 )

Date of Publication:

Dec 1999

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