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A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD

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3 Author(s)
O. E. Erdogan ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; P. J. Hurst ; S. H. Lewis

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise+distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm2 in 1.5-μm CMOS

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 12 )