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A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2

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2 Author(s)
Hoogzaad, G. ; Philips Res. Lab., Eindhoven, Netherlands ; Roovers, R.

This paper describes the design of a 10-bit, 40-MSample/s analog-to-digital converter (ADC) based on a cascaded folding and interpolating architecture. The folding and interpolating factors are optimized for low power. The ADC features balanced circuit design, a newly developed shifted averaging technique, and stacked circuits for analog and digital folding. The untrimmed ADC dissipates 65 mW from a single 5-V supply. The fully differential ADC achieves 9.2 effective bits for a 1.6-Vpp input signal. Its resolution bandwidth is 20 MHz. The ADC is realized in a 7-GHz, 0.6-μm BiCMOS process and measures 0.8 mm2

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 12 )