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A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist

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2 Author(s)
Brandt, B.P. ; Nat. Semicond. East Coast Labs., Salem, NH, USA ; Lutsky, J.

A CMOS subranging analog-to-digital converter (ADC) incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal ill-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADC's with differential inputs and significantly better than those with single-ended inputs. The typical maximum differential nonlinearity is ±0.4 LSB, and the maximum integral nonlinearity is ±0.55 LSB without trimming or calibration. With an ADC power of 55 mW plus an SHA power of 20 mW from a 5-V supply, the active area is 1.6 mm2 in a 0.5-μm double-poly, double-metal CMOS technology

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 12 )