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A Nyquist-rate pipelined oversampling A/D converter

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5 Author(s)
S. A. Paul ; Lincoln Lab., MIT, Lexington, MA, USA ; H. -S. Lee ; J. Goodrich ; T. F. Alailima
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A pipelined Δ-Σ analog-to-digital-converter architecture is described that incorporates the high speed of pipelined converters and the high resolution of oversampling quantization. A prototype, containing both modulation and decimation circuits on a single chip, is implemented using a 1.2-μm commercial CMOS process. It uses charge-coupled-device elements to perform pipelined analog operations. It exhibits a maximum data rate of 18 MHz, a signal-to-noise ratio of 74 dB, spurious-free dynamic range of 78 dB, differential nonlinearity of <0.15 LSB at 13 bits, and power dissipation of 324 mW

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 12 )