Application of defect inspection in development of 0.25 and 0.18 micron technology

We present a general strategy for identifying systematic and random defect issues during the initial stages of development of 0.25 /spl mu/m and 0.18 /spl mu/m logic technology. This strategy includes Critical Area Analysis modeling, improved defect monitoring techniques, methodology for prioritizing tools for continuous improvement to reduce random particles, and the use of back-end-of-line monitors. Technology development requires stringent attention to systematic defects, which dominate early yield learning. For all defect issues, we discuss practical aspects of inspection tool recipe sensitization which optimize the capture rate of visual yield limiters, enabling fast feedback problem resolution and high confidence matching of electrical faults and physical defects.