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IC performance prediction for test cost reduction

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5 Author(s)
Jungran Lee ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Walker, D.M.H. ; Milor, L. ; Yeng Peng
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This paper describes a methodology for building models predicting manufactured integrated circuit performances as a function of inline and wafer electrical test measurements. We show how these predictions can be used to predict the performance of an industrial microprocessor, and reduce the average number of speed bins that must be tested by 45%

Published in:

Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on

Date of Conference:

1999