By Topic

Synthesis of arrays and records

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jha, P.K. ; EDA Lab., IBM Corp., East Fishkill, NY, USA ; Barnfield, S. ; Weaver, J. ; Mukherjee, R.
more authors

The use of arrays and records in modern hardware-description languages (HDL) allows designs to be modeled at very high levels of abstraction. However, the support for these complex data types in current synthesis tools is very limited. This paper presents a comprehensive scheme to synthesize aggregate data types such as arrays and records, in a very general manner. The approach consists of mapping objects (variables and signals) of aggregate data types onto one-dimensional vectors, and generating specialized addressing/decoding hardware to be able to access any field of the data type. Arrays of multiple dimensions and any level of nesting of arrays and records are supported. This paper describes the whole process, from the language specification to the actual hardware structures created by synthesis

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference: