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Using an embedded processor for efficient deterministic testing of systems-on-a-chip

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2 Author(s)
A. Jas ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; N. A. Touba

If a system-on-a-chip (SOC) contains an embedded processor, the paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The basic idea is that the tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. This approach both reduces the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e. a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate that a significant amount of compression can be achieved

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Computer Design, 1999. (ICCD '99) International Conference on

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