By Topic

Fault simulation based test generation for combinational circuits using dynamically selected subcircuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Reddy, S.M.

We propose a fault simulation based method to generate test patterns that achieve high fault coverages for combinational circuits. Due to the use of fault simulation, the proposed method is scalable and can be applied to large designs. The unique feature of the proposed method is that it uses a dynamic circuit partitioning scheme. Under this scheme, test patterns are generated so as to activate and propagate faults within specific subcircuits. The circuit is first partitioned statically. If it turns out that certain areas of the circuit still contain undetected faults, additional sub-circuits are added to the originally selected ones in order to better cover these areas. We present experimental results using stuck-at faults and bridging faults as the fault model driving the dynamic partitioning scheme

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference: