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Design for testability to combat delay faults

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1 Author(s)
Savir, J. ; Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. The paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999