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Multi-level logic minimization through fault dictionary analysis

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2 Author(s)
Mehler, R.W. ; Texas Univ., Dallas, TX, USA ; Mercer, M.R.

Presents the results of the study of a new algorithm for multi-level logic minimization. The study is based on the premise that an untestable node is a redundant node, and that nodes that do not demonstrably cause conflicting behavior at primary outputs may be compatible. Data gathered using the presented techniques show that fault dictionary analysis is a powerful tool for logic minimization. The algorithm developed in this study, the Texas Aggies Logic Optimizing Netlister (TALON), is shown to be competitive with, and complementary to, other methodologies. TALON can be used by itself or as a preprocessor or postprocessor for other tools, giving superior results to those obtained by any of them working independently

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999

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