System-on-a-chip bus architecture for embedded applications

Increasing levels of on-chip system integration means that more functional units need to be interconnected. To limit design effort and to allow for future reuse, this interconnection should be kept as simple and generic as possible. The need to limit clock cycle times and power consumption means that bus capacitance must be as low as possible. This can be done effectively by partitioning functional units onto discrete bus connections that are jointed by bus bridges. The paper describes the evolution of ARM system chip architectures of steadily increasing complexity and details a state-of-the-art design.