A regular layout structured multiplier based on weighted carry-save adders

A new parallel array multiplier based on a new circuit called a weighted carry-save adder (WCSA) is presented in this paper. Each row of the array consists of a (n+3) bit carry-save adder and one WCSA. Since the proposed WCSA enables the multiplier to be very regular as well as to have less operation complexity at the final addition stage than that of conventional implementations, the proposed WCSA is better suited for hardware implementation. Compared with the previous implementations, the proposed multiplier yields an area reduction of 21% for 64/spl times/64 multiplication. A 16/spl times/16 multiplier implemented in 0.8 /spl mu/m CMOS DLM technology functions at more than 60 MHz. The chip is 1.04/spl times/1.15 mm/sup 2/ with 7877 transistors.