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Low-power radix-4 combined division and square root

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2 Author(s)
Nannarelli, A. ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; Lang, T.

Because of the similarities in the algorithm it is quite common to implement division and square root in the same unit. The purpose of this work is to implement a low-power combined radix-4 division and square root floating-point double precision unit and to compare its performance and energy consumption with a radix-4 division only unit. Previous work has been done on reducing the energy dissipated in a divider. Here we apply the same techniques to the combined division and square root unit and consider modifications and tradeoffs. Results show that the energy dissipation for the combined division/square root unit can be reduced by about 35% without affecting the latency and an additional 20% reduction can be obtained using a dual voltage. Moreover the unit is 5% slower than a divider and its energy dissipation is 15% higher

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999