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Performance evaluation of configurable hardware features on the AMD-K5

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2 Author(s)
M. Clark ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; L. K. John

Many modern processors incorporate certain configurable hardware features, although these features are never publicized. For instance, the AMD-K5 incorporates the ability to disable branch prediction, put caches into write allocate mode, etc. The ability to configure the features by software combined with the availability of on-chip performance counters allow the direct measurement of the performance of these features an real benchmarks running with real operating systems. This paper evaluates several configurable features that exist on the AMD-K5 processor using industry standard benchmarks. The features evaluated in this research are (i) cache predecode (ii) branch prediction, (iii) write allocate mode, and (iv) speculative loads bypassing stores. These features are evaluated on a benchmark suite that was relevant when K5 debuted (Winstone 96), as well as two subsequent benchmark suites (Winstone 97 and 98). This allows an evaluation of how the features have performed as software has progressed. The results show that write allocate was a big performance improvement on Winstone benchmarks, almost equal to the value of branch prediction, The bypassing loads feature did nor return much in performance and the continuation of speculative predecode did not really help until Winstone 98. It was also interesting that all features showed positive improvement on Winstone 98. We feel that understanding the performance implication of these features and how they have matured over time gives us an increased insight into the future design of microprocessors and how application code is evolving

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Computer Design, 1999. (ICCD '99) International Conference on

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