By Topic

Design methodology for a one-shot Reed-Solomon encoder and decoder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Morioka, S. ; Tokyo Res. Lab., IBM Res., Kanagawa, Japan ; Katayama, Y.

The design methodology for a high-performance and compact one-shot Reed-Solomon encoder/decoder realized as a combinational circuit is presented. Under a two-level optimization approach, a combination of new encoding/decoding algorithms enabling highly parallel, yet shared architecture, and logic optimization methods tuned for huge-scale Galois field arithmetic operations, improves the circuit size and speed significantly. The higher level optimization not only can be entirely independent of the gate level optimization, but also further augments the advantages in the gate level optimization. As a result a (40-34,32)RS encoders/decoder soft IP-core achieving 45 ns latency and >7 Gb/s peak throughput without pipelining is realized using <90 K cells under 0.35 um CMOS gate-array technology

Published in:

Computer Design, 1999. (ICCD '99) International Conference on

Date of Conference:

1999