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A content addressable memory using Josephson junctions

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3 Author(s)
Morisue, M. ; Dept. of Electron. Eng., Saitama Univ., Japan ; Kaneko, M. ; Hosoya, H.

A content-addressable memory circuit using Josephson nondestructive readout (NDRO) memory cells is described. The memory circuit proposed performs searching functions, such as coincidence, incoincidence, and don't-care functions, in addition to the conventional memory function of writing and reading. This memory circuit is able to achieve the 'less than' function in addition to the three functions listed above. Computer simulation of a 3-word by 3-b memory was used to investigate how high-performance operation can be achieved. The simulation results show that the four operations for all combinations of binary inputs have been achieved with a cycle time of less than 80 ps and a 0.28- mu W/cell dissipation. The simulation results also show the design tolerances of the gate currents of four superconducting quantum interference device (SQUID) gates used in the memory circuit to range from 25% to 17%.<>

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Applied Superconductivity, IEEE Transactions on  (Volume:1 ,  Issue: 1 )