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Evaluating register allocation and instruction scheduling techniques in out-of-order issue processors

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2 Author(s)
Valluri, M.G. ; Lab. for Comput. Archit., Texas Univ., Austin, TX, USA ; Govindarajan, R.

The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time. We evaluated four existing techniques, namely postpass scheduling, prepass scheduling, parallel interference graph, and integrated prepass scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time

Published in:

Parallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on

Date of Conference:

1999

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