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An implementation approach for wide-bandwidth digital quadrature demodulators intended for high performance radar and electronic warfare applications is presented. An overview of design tradeoffs made to reduce the data processing rate and cost are given, as are architectural considerations specific to FPGA implementation of digital filtering operations. A design example for processing input signals having an intermediate frequency of 160 MHz and a bandwidth of /spl sim/45 MHz is presented. This performance is achieved with a low-cost Xilinx 4000E series FPGA with a -3 speed grade. A very high internal resource utilization of 83% was attained while meeting stringent timing requirements via the use of computationally efficient signal processing algorithms, thorough logic optimization, and careful mapping of signal processing algorithms to hardware. Simulation results obtained for faster FPGA families and speed grades indicate that a doubling in the processing rate could be reached with few design modifications.