By Topic

Timing analysis including clock skew

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Harris, D. ; Harvey Mudd Coll., Claremont, CA, USA ; Horowitz, M. ; Liu, D.

Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to budget less skew between nearby elements than across the entire die, but current timing analysis algorithms do not handle correlated clock skews. This paper extends the Sakallah-Mudge-Olukotun (SMO) latch-based timing analysis to include different amounts of clock skew between different elements. The key change is that departure times from each latch must be defined with respect to launching clocks so that the skew between the launching and receiving clocks can be determined at each receiver. The exact analysis leads to an explosion in the number of timing constraints, but most constraints are not tight in practical situations and a modified version of the Szymanski-Shenoy relaxation algorithm gives exact results with only a small increase in runtime. The timing analysis formulation also captures the effects of skew on edge-triggered flip-flops, domino circuits, and min-delay constraints. Our exact algorithm, applied to a supercomputer node controller with over 12000 clocked elements, finds the system can run 50-90 ps faster than a single skew analysis would predict and requires searching fewer than 4% more latch departures than conventional algorithms. With the less conservative skew budgets enabled by better timing analysis, we expect clocked systems will remain viable to multi-GHz frequencies

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:18 ,  Issue: 11 )