A reuse oriented design methodology for artificial neural networks implementation

This paper describes a new reuse oriented design methodology for artificial neural networks (ANNs) implementation. The proposed approach is mainly based on a VHDL synthesis environment that uses a pre-designed hierarchical and parametric library suited for different ANN topologies. To validate this approach, a case study of the three-layer back-propagation algorithm is illustrated, A VHDL description of a (5-3-2) ANN circuit is passed through synthesis tool, GALILEO for FPGA implementation. The preliminary results are very successful, since the whole network has been implemented onto only one FPGA. It has a clock frequency of about 16 MHz and can be used in some real time applications.