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A modular and scalable architecture for the realization of high-speed programmable rank order filters

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3 Author(s)
Hatirnaz, I. ; Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA ; Gurkaynak, F.K. ; Leblebici, Y.

We present a new scalable architecture for the realization of fully programmable rank order filters (ROF), based on Capacitive Threshold Logic (CTL) gates. Variants of ROFs, especially median filters, are widely used in digital signal and image/video processing and image enhancement. The CTL-based realization of the majority gates used in the ROF architecture allows the filter rank and the window size to be user-programmable, using a much smaller silicon area, compared to conventional realizations of digital median filters. The proposed filter architecture is completely modular and scalable, and the circuit complexity grows only linearly with maximum window size and with word length. Detailed post-layout simulations of the ROF prototype circuit indicate that the new architecture can accommodate sampling clock rates of up to 50 MHz, corresponding to an effective data processing rate of 800 Mb/s for a filter with window size 63 and word length of 16 bits

Published in:

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Date of Conference:

1999

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