By Topic

Low power parallel multiplier design for DSP applications through coefficient optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sangjin Hong ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Suhwan Kim ; Papaefthymiou, M.C. ; Stark, W.E.

Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers

Published in:

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Date of Conference: