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A universal march pattern generator for testing embedded memory cores

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3 Author(s)
Wei-Lun Wang ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Kuen-Jong Lee ; Jhing-Fa Wang

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator

Published in:

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Date of Conference:

1999