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ATLAS II: optimizing a 10 Gbps single-chip ATM switch

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2 Author(s)
Pnevmatikatos, D. ; Inst. of Comput. Sci., Found. for Res. & Technol.-Hellas, Crete, Greece ; Kornaros, G.

We describe ATLAS II, an optimized version of the ATLAS I ATM switch. While in ATLAS I we concentrated on correctness, in ATLAS II we concentrate on optimizing the area and the performance of the switch. To achieve these goals we utilize improved design techniques and circuitry, and we eliminate functionalities of marginal benefit. Our results show that we can achieve significant performance and cost benefits, requiring only a small increment in manpower

Published in:

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Date of Conference:

1999