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An integrated approach to data path synthesis for power optimization

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3 Author(s)
Chaeryung Park ; Synopsys Inc., Mountain View, CA, USA ; Taewhan Kim ; Liu, C.L.

This paper presents an integrated approach to data path synthesis which solves three important design problems: scheduling, allocation, and hardware partitioning with power minimization as a key design objective. Based on the rules of thumbs introduced in prior work on synthesis for low power we derive an integer programming formulation for solving the problems. We then, based on the formulation, develop an efficient algorithm which performs scheduling, allocation and hardware partitioning simultaneously so that the effects of them on power consumption are exploited more fully and effectively. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption

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ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

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