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Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs

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7 Author(s)
D. L. Kencke ; Microelectron. Res. Center, Texas Univ., Austin, TX, USA ; W. Chen ; H. Wang ; S. Mudanai
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High permittivity (K) gate insulators are projected for sub-100 nm Si MOSFETs since direct tunneling will likely limit SiO/sub 2/ thicknesses to 1.0-1.5 nm. High-K insulators avoid tunneling, but their larger physical thicknesses introduce subtle capacitive coupling phenomena such as fringing-induced barrier lowering (FIBL) that can compromise off-state leakage. In this study, device simulation examines both on and off-state drain current with very high-K gate insulators and sidewall spacers to reveal new source-side and boundary condition effects. Asymmetric devices help to distinguish the effects. A study of stacked gate insulators demonstrates a 10% increase in drive current achieved with high-K spacers in 50 nm devices.

Published in:

Device Research Conference Digest, 1999 57th Annual

Date of Conference:

23-23 June 1999