Referenced Items are not available for this document.
Delay testing of designs that contain intellectual property (IF) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it robustly tests selected paths without using extra logic, and, at the same time, protects the intellectual property
Published in:
Test Conference, 1999. Proceedings. International
Date of Conference: 1999
- Page(s):
- 1045 - 1054
- Meeting Date :
- 28 Sep 1999-30 Sep 1999
- ISSN :
- 1089-3539
- Print ISBN:
- 0-7803-5753-1
- INSPEC Accession Number:
- 6543624
- Conference Location :
- Atlantic City, NJ
- Digital Object Identifier :
- 10.1109/TEST.1999.805838
- Product Type:
- Conference Publications
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