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A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming

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2 Author(s)
H. B. Kim ; Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; D. S. Ha

A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high-level BIST synthesis methods perform the tasks sequentially at the cost of global optimality. We proposed a new approach based on an integer linear programming (ILP). Our method achieves optimal solutions for most circuits in hardware overhead, but it takes a long processing time. In this paper, we present a heuristic method to address this problem. The heuristic partitions a given data flow graph into smaller regions based on control steps and applies the ILP for each region successively. Our heuristic reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised. We present experimental results for six circuits and compare the results with other BIST synthesis methods

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Test Conference, 1999. Proceedings. International

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