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An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques

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2 Author(s)
Seshadri, S. ; Mentor Graphics Corp., Warren, NJ, USA ; Hsiao, M.S.

This research applies formal dataflow analysis and techniques to high-level DFT. Our proposed approach improves testability of the behavioral-level circuit description (such as in VHDL) based on propagation of the value ranges of variables through the circuit's Control-Data Flow Graph (CDFG). The resulting testable circuit is accomplished via controllability and observability computations from these value ranges and insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a minimum

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Test Conference, 1999. Proceedings. International

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