Skip to Main Content
Timing skew has been the major limitation for high-speed synchronous operation of a VLSI system. In this paper, a statistical timing model that accounts for both static and random timing skew is proposed. Based on this model, we analyze the timing rules of a synchronous VLSI system consisting of multiple pipelined stages, establish the yield of the system as a function of its device characteristics, and derive the relationship between the maximum throughput of such a system and its timing skew. The following timing schemes are evaluated: conventional pipelining, in which the transmitter cannot initiate the next cycle until the receiver has received the data and wave pipelining, in which the transmitter initiates the next cycle as soon as the current data has been sent out. The results show that the yield of a VLSI system using either of the pipelining schemes exhibits threshold behavior for Gaussian distributed static skew. Furthermore, the system throughput is shown to be very sensitive to the random skew.