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Low-energy CSMT carry generators and binary adders

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1 Author(s)
K. K. Parhi ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

This paper presents novel hybrid carry-select modified-tree (CSMT) adder architectures for binary carry generators and adders using multiplexers only. These architectures not only require the fewest number of multiplexers, but also consume the least energy for a specified latency. These architectures are based on a carry-select configuration where each block can be a carry-select or tree or modified-tree block. The modified-tree blocks permit ripple in the carry-generation process; which leads to dramatic reduction in the number of multiplexers as well as power consumption. It is shown that, for a block length W, the carry-select block and the modified-tree block with internal ripple of (log/sub 2/ W-1) multiplexer stages require the same number of multiplexers. This is a powerful result because the longer carry-select blocks can be replaced by the modified-tree blocks without increasing the multiplexer complexity. The advantage of this approach is in reduction of power consumption since the amount of ripple in the carry-select block grows linearly with W, while that in the modified-tree block grows logarithmically with W. It is shown that for fastest adder/subtractor designs, the proposed CSMT architecture can reduce the multiplexer complexity by about 40% for word-lengths ranging from 8 to 32, when compared with known tree approaches. It is shown that, for a certain specified latency and specified number of multiplexers, a family of carry-select and CSMT adders can be designed. It is shown that, for a specified latency, the carry-select adders with larger number of blocks and smaller block lengths consume less power. Through extensive simulations, CSMT adder configurations that minimize energy consumption or power-latency product, which are approximately 5% to 10% less than those of known tree and best carry-select adders, are obtained. Finally, based on novel latency-matching and block-increment techniques introduced in this paper, a systematic design methodology for design of CSMT adders with least latency, least number of multiplexers, and least energy consumption is presented.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:7 ,  Issue: 4 )