By Topic

Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Min Xu ; Y Explorations Inc., Irvine, CA, USA ; Kurdahi, F.J.

The importance of efficient area and timing estimation techniques is well-established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on the gate and/or literal count. Those models are not accurate enough to allow effective design space exploration since the effects of interconnect can indeed dominate the final design cost. The situation becomes even worse when the design is targeted to field-programmable gate array (FPGA) technologies since the wire delay may contribute up to 60% of the overall design delay. In this paper, we present an approach of estimating area and timing for lookup-table-based FPGAs that takes into account not only gate area and delay, but also the wiring effects. We select the Xilinx XC4000 series as our main concentration because of their popularity. We tested our estimator with several benchmarks and the results show that we receive accurate area and timing estimates efficiently.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:7 ,  Issue: 4 )