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DFT advances in the Motorola's MPC7400, a PowerPCTM G4 microprocessor

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8 Author(s)
Pyron, C. ; Somerset Design Centre, Austin, TX, USA ; Alexander, M. ; Golab, J. ; Joos, G.
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Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market

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Test Conference, 1999. Proceedings. International

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