A scalable priority queue manager architecture for output-buffered ATM switches

We describe a scalable priority queue manager that implements deadline-ordered service disciplines in an output-buffered ATM switch, which can be used as a switching node in high-speed packet switched networks to provide quality of service (QoS) guarantees. The priority queue manager can handle a range of priority levels from 0 to (2¹⁶ -1), a buffer size of 64 k ATM cells, and 16 input links at 2.5 Gb/s. Two main components of the priority queue manager are: (1) a VLSI chip for searching the highest priority levels stored in the queue and for managing queues; (2) standard off-the-shelf SRAMs for cell buffering. In addition, we propose three architectures that combine the priority queue managers to scale up buffer size, number of input links, and bandwidth. We show that a combination of priority queue managers can yield a buffer size of 16 M ATM cells, 256 input links, and 5.8 Gb/s bandwidth