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A model of the distribution of interconnectivity through multiple system levels and the impact of different design strategies and IP re-use on design effort

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2 Author(s)
Palmer, P.J. ; Dept. Manuf. Eng., Loughborough Univ., UK ; Williams, D.J.

The equation for design effort derived by Ueda et al (1996) is used as a starting point for the development of a model of design effort in hierarchical electronic systems. The fundamental assertion is that design effort can be regarded as a function of the number of modules that have to be interconnected. This paper also introduces a measure of system hierarchy and the impact of this measure on systems of different sizes explored. The model is then developed to include any number of system levels. A numerical exploration of the model shows that for any hierarchical system there is an optimum degree of modularity that minimises design effort. The model is extended to encompass the impact of design re-use and suggests that the conditions for maximum benefits of design re-use require greater hierarchy than systems with no re-use. The model results indicate that the relationship between cost and system complexity is geometric in nature and in this sense is compatible with those of other attempts to model design costs. The partitioning of a system into modules is typically decided at an early stage of the design process. These decisions are shown to have a major impact on design cost, but are difficult to alter once the design work has been started. We conclude that there is a need for design tools to evaluate the cost impact of partitioning decisions at a very early stage in the design process and a need to include the impact of system structure in cost estimation models

Published in:

Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT

Date of Conference:

1999