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This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach concerns the XILINX4000 family. On this example of FPGA, a classical test technique consists in first generating test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m/spl times/m array of logic cells. In this classical technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.
European Test Workshop 1999. Proceedings
Date of Conference: 25-28 May 1999