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High-level path activation technique to speed up sequential circuit test generation

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2 Author(s)
Raik, J. ; Tallinn Tech. Univ., Estonia ; Ubar, R.

In current paper, a novel high-level symbolic path activation technique for sequential circuit test generation is proposed. The technique has been implemented as a part of a hierarchical ATPG tool which utilizes internal representation of multi-level (register-transfer and structural levels) decision diagram models. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time.

Published in:

European Test Workshop 1999. Proceedings

Date of Conference:

25-28 May 1999