By Topic

Nanometer technology effects on fault models for IC testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Aitken, R.C. ; Agilent Technol., Palo Alto, CA, USA

Accepted methods for testing integrated circuits, such as the fault models examined here, require ongoing research and continual adaptation to accommodate increasing circuit size, growing defect subtlety, and less varied manufacturing processes

Published in:

Computer  (Volume:32 ,  Issue: 11 )