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Nanometer technology effects on fault models for IC testing

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1 Author(s)
R. C. Aitken ; Agilent Technol., Palo Alto, CA, USA

Accepted methods for testing integrated circuits, such as the fault models examined here, require ongoing research and continual adaptation to accommodate increasing circuit size, growing defect subtlety, and less varied manufacturing processes

Published in:

Computer  (Volume:32 ,  Issue: 11 )