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Rethinking deep-submicron circuit design

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2 Author(s)
Sylvester, D. ; Synopsys Inc., USA ; Keutzer, K.

Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs

Published in:

Computer  (Volume:32 ,  Issue: 11 )