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In multichannel telecommunication networks, switching systems, and processor-memory interconnects, the need for conflict-free traffic assignment arises whenever packets (or requests) are to be directed from input buffers (processors) to specific outlets (modules). This paper presents an algorithm, based on forward planning, which can be used in the above-mentioned applications for scheduling conflict-free transfers of packets from inputs to outputs. The performance of the algorithm is evaluated in the sense of throughput and delay and is compared with that of system of distinct representatives (SDR), an earlier proposed algorithm featuring 100% assignment efficiency. Then, its worst-case computational complexity is compared with that of SDR and several suboptimal (but low complexity) algorithms reported in literature. The proposed forward planning algorithm is shown to have the lowest order of computational complexity and permits simpler buffer organization and access modes. Moreover, it is shown that forward planning of packet transmissions offers significant performance improvements if the finite capacity of buffers is taken into account.