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Increase the behavioral fault model accuracy using high-level synthesis information

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4 Author(s)
Brera, M. ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; Ferrandi, F. ; Sciuto, D. ; Fummi, F.

This paper describes an approach for enhancing the effectiveness of behavioral test generation by considering high-level and logic synthesis information to increase the correlation between the behavioral fault model and the stuck-at-fault model. In particular we mainly consider two types of information: the mapping between high-level operators and RTL modules and the type of gate level implementation adopted by the RTL modules

Published in:

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Date of Conference:

Nov 1999

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