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The design of software-based algorithms for fast IP address lookup targeted for general purpose processors has received tremendous attention in recent years due to its low cost implementation and flexibility. However, all work to date fails to account for the hierarchical memory structure of the processor when designing algorithms. In this work, we propose a dynamic memory model that captures data movement between hierarchical memories and the memory access cost. Using the model, we formulate the design of IP address lookup algorithms as a well-defined optimization problem that minimizes an algorithm's average lookup time. We first show the problem is NP-hard. We then present an optimization framework and associated algorithm based on Lagrange multipliers that terminates in a bounded-error solution. Simulation shows the synthesized algorithm has noticeable performance gain over existing techniques.
Date of Conference: 31 Oct.-3 Nov. 1999