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Error recovery in shared memory multiprocessors using private caches

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3 Author(s)
K. -L. Wu ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; W. K. Fuchs ; J. H. Patel

The problem of recovering from processor transient faults in shared memory multiprocessor systems is examined. A user-transparent checkpointing and recovery scheme using private caches is presented. Processes can recover from errors due to faulty processors by restarting from the checkpointed computation state. Implementation techniques using checkpoint identifiers and recovery stacks are examined as a means of reducing performance degradation in processor utilization during normal execution. This cache-based checkpointing technique prevents rollback propagation, provides rapid recovery, and can be integrated into standard cache coherence protocols. An analytical model is used to estimate the relative performance of the scheme during normal execution. Extensions to take error latency into account are presented

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:1 ,  Issue: 2 )